1. Field of the Invention
In general, the present invention relates to an image displaying apparatus as well as an image displaying method adopted by the image displaying apparatus, and can be applied typically to an image displaying apparatus adopting an active matrix driving technique provided for organic EL (Electro Luminescence) devices employed in the image displaying apparatus. In particular, the present invention relates to an image displaying apparatus capable of preventing horizontal-direction cords from being generated on the screen of the image displaying apparatus in order to effectively eliminate deteriorations of the quality of an image being displayed on the screen during simultaneous execution of a process of compensating pixel circuits for variations of threshold voltage of driving transistors employed in the pixel circuits on a plurality of pixel-matrix rows at the same time by swapping a timing to carry out a gradation-voltage setting operation on any specific pixel-matrix row as an operation lagging behind the threshold-voltage variation compensation process, which has been carried out on all pixel-matrix rows at the same time, with a timing to carry out a gradation-voltage setting operation on a pixel-matrix row adjacent to the specific pixel-matrix row as an operation lagging behind the threshold-voltage variation compensation process, and relates to an image displaying method adopted by such an image displaying apparatus in a time-axis direction and/or a scan-line direction.
2. Description of the Related Art
The related image displaying apparatus adopting an active matrix driving technique making use of organic EL (Electro Luminescence) devices is provided with an image displaying section created by arranging pixel matrixes, which each have an organic EL device and a transistor for driving the organic EL device, to form a pixel matrix. In addition, the related image displaying apparatus also includes a signal-line driving circuit and a scan-line driving circuit, which are provided at locations surrounding the image displaying section, to serve as circuits for driving the pixel circuits in order to display a desired image on the image displaying section.
With regard to the image displaying apparatus making use of organic EL (Electro Luminescence) devices, Japanese Patent Laid-open No. 2005-345722 proposes a method for assuring a high quality of the image even if a driving transistor of the N-channel type is employed to serve as a transistor for driving an organic EL device in every pixel circuit. The method is capable of assuring a high quality of the image by compensating a pixel circuit for variations of the threshold voltage of the driving transistor in the pixel circuit from transistor to transistor in a process of setting a gradation in the pixel circuit in order to get rid of luminance variations caused by the variations of the threshold voltage to appear as variations of the luminance of light emitted by the organic EL device employed in the same pixel circuit from pixel to pixel.
In addition, Japanese Patent Laid-open No. 2007-133284 discloses a configuration in which processing to compensate a pixel circuit for variations of the threshold voltage of the driving transistor employed in the pixel circuit is carried out a plurality of times by dividing the processing into a plurality of processes each executed in a period.
A drain-source current Ids flowing through every driving transistor employed in the image displaying apparatus of the type described above to serve as a transistor for driving the organic EL device serving as an LED (light emitting device) in the image displaying apparatus can be expressed by equations given as follows:Ids=β/2·(Vgs−Vth)β=μ·W/L·Cox  (1)
In the above equation, reference notation Vgs denotes a voltage applied between the gate and source electrodes of the driving transistor, reference notation μ denotes the mobility of the driving transistor, reference notation W denotes the channel width of the driving transistor, reference notation L denotes the channel length of the driving transistor, reference notation Cox denotes the capacity per unit area of the gate insulating film of the driving transistor and reference notation Vth denotes the threshold voltage of the driving transistor.
Thus, in an operation to drive the organic EL device in accordance with the drain-source current Ids of the driving transistor by setting the gate-source voltage Vgs of the transistor, even for the same set magnitude of the gate-source voltage Vgs, the drain-source current Ids varies from transistor to transistor due to an effect given by variations in threshold voltage Vth from transistor to transistor. As a result, the luminance of light emitted by the organic EL device also varies from pixel to pixel as well.
Reference notations Iref and Vref are substituted into Equation (1) given above to serve as replacements for reference notations Ids and Vgs respectively and, then, an equation obtained as a result of the substitution is rewritten into Equation (2) given as follows.Vref=(Iref/(β/2))1/2+Vth  (2)
Let a voltage difference of (Vdata−Vref) be a difference in voltage between a voltage Vdata representing the luminance of light emitted by the organic EL device and the voltage Vref expressed by Equation (2). Next, the voltage difference of (Vref−Vdata) is substituted into Equation (1) to serve as a replacement for reference notation Vgs and, then, the right-hand expression of Equation (2) is substituted into an equation obtained as a result of the substitution of the voltage difference of (Vref Vdata)to serve as a replacement for reference notation Vref to result in Equation (3) given as follows:Ids=β/2·(Vdata−(Iref/β/2))1/2)2  (3)
It is obvious that Equation (3) no longer includes the term of the threshold voltage Vth, implying that the drain-source current Ids does not vary from transistor to transistor due to variations in threshold voltage Vth and, hence, the luminance of light emitted by the organic EL device can be prevented from varying from pixel to pixel due to variations in drain-source current Ids. Thus, by applying a bias determined by the voltage Vref to the gate-source voltage Vgs of the driving transistor and a bias determined by the current Iref to the drain-source current Ids flowing through the driving transistor, it is possible to get rid of luminance variations caused by the variations of the threshold voltage Vth of the driving transistor to appear as variations of the luminance of light emitted by the organic EL device employed in the same pixel circuit as the driving transistor from pixel to pixel. It is to be noted that each of the voltage Vref and the current Iref, which are used in Equation (2), has a constant magnitude determined by the characteristic of the driving transistor which drives the organic EL device employed in the same pixel circuit as the driving transistor.
If the current Iref is set at 0 (that is, Iref=0), from Equation (2), the voltage Vref becomes equal to Vth (that is, Vref=Vth). With Iref set at 0, Equation (3) is simplified into the following equation:Ids=β/2·(Vdata)2 
Also in this case, it is obvious that the above equation no longer includes the term of the threshold voltage Vth, implying that the drain-source current Ids does not vary from transistor to transistor due to variations in threshold voltage Vth and, hence, the luminance of light emitted by the organic EL device can be prevented from varying from pixel to pixel due to variations in drain-source current Ids. That is to say, with the current Iref set at 0, by merely applying a bias Vref to the gate-source voltage Vgs of the driving transistor as indicated by the above equation, the pixel circuit can be compensated for luminance variations caused by the variations of the threshold voltage Vth of the driving transistor to appear as variations of the luminance of light emitted by the organic EL device employed in the same pixel circuit as the driving transistor from pixel to pixel. Each of Japanese Patent Laid-open No. 2005-345722 and Japanese Patent Laid-open No. 2005-133284, which are mentioned before, discloses a method based on this principle as a method for compensating the pixel circuit for luminance variations caused by the variations of the threshold voltage Vth of the driving transistor to appear as variations of the luminance of light emitted by the organic EL device employed in the same pixel circuit as the driving transistor from pixel to pixel.
FIG. 17 is a block diagram showing interconnections of sections employed in an image displaying apparatus 1 disclosed in Japanese Patent Laid-open No. 2007-133284. As shown in the block diagram, the image displaying apparatus 1 also employs a signal-line driving circuit 3 which includes a horizontal selector (HSEL) 2. In addition, the image displaying apparatus 1 employs a scan-line driving circuit 5 which includes a write scanner (WSCN) 4A and a drive scanner (DSCN) 4B.
The horizontal selector 2 employs a plurality of latch circuits for sequentially latching input image data D1. Each of the latch circuits is provided for one of signal lines SIG connected to the image displaying section 6. The input image data D1 latched in the latch circuits is apportioned to the signal lines SIG. The input image data D1 to be apportioned to any one of the signal lines SIG is converted into an analog signal in a digital-to-analog conversion process and asserted to the signal line SIG to serve as one of signal-line driving signals Ssig which sequentially show gradations of pixel circuits connected to the signal lines SIG. The horizontal selector 2 outputs the signal-line driving signal Ssig to a signal line SIG for which the signal-line driving signal Ssig is generated.
Each of the write scanner 4A and the drive scanner 4B sequentially transfers a reference signal generated by a signal generation circuit not shown in the block diagram of FIG. 17 to scan lines to serve as a write scan-line driving signal WS and a drive scan-line driving signal DS respectively. To be more specific, the write scanner 4A asserts the write scan-line driving signal WS on a write scan line connected to the gate electrode of each signal writing transistor TR5 on a row corresponding to the write scan line whereas the drive scanner 4B asserts the drive scan-line driving signal DS on a drive scan line connected to the gate electrode of each power switching transistor TR2 on a row corresponding to the drive scan line.
The image displaying section 6 includes predetermined pixel circuits 7 which are arranged to form a pixel matrix. Each of the pixel circuits 7 has an NMOS transistor TR1 for driving an organic EL device 8 which serves as an LED (Light Emitting Device) driven by a drain-source current Ids generated by the NMOS transistor TR1. In the following description, the NMOS transistor TR1 is also referred to as a driving transistor TR1. The gate and source electrodes of the driving transistor TR1 functioning as a source follower are connected respectively to the two terminals of a signal-level holding capacitor C1. In the block diagram of FIG. 17, reference notation Cp denotes a capacitive component of the organic EL device 8 whereas reference notation Vss1 denotes a cathode voltage which is a voltage applied to the cathode electrode of the organic EL device 8.
The drive scan-line driving signal DS generated by the drive scanner 4B is applied to the gate of an NMOS transistor TR2 also referred to hereinafter as a power switching transistor in order to put the power switching transistor TR2 in a state of being turned on or off in accordance with the drive scan-line driving signal DS. The drain electrode of the power switching transistor TR2 is connected to a driving power supply for supplying a power-supply voltage Vdd. In the pixel circuit 7, with the power switching transistor TR2 controlled to enter a state of being turned on by the drive scan-line driving signal DS, the power supply generating the power-supply voltage Vdd supplies a current to the driving transistor TR1 by way of the power switching transistor TR2 and the driving transistor TR1 may forward the current to the organic EL device 8 as the drain-source current Ids mentioned above. With the power switching transistor TR2 controlled to enter a state of being turned off by the drive scan-line driving signal DS, on the other hand, the current supplied to the driving transistor TR1 by way of the power switching transistor TR2 is cut off so that the drain-source current Ids flowing to the organic EL device 8 is also cut off as well. In this way, the organic EL device 8 can be controlled to enter a state of emitting light or emitting no light in accordance with whether or not the drain-source current Ids is flowing to the organic EL device 8.
The write scan-line driving signal WS generated by the write scanner 4A is applied to the gate of an NMOS transistor TR5 also referred to hereinafter as a signal writing transistor in order to put the signal writing transistor TR5 in a state of being turned on or off in accordance with the drive scan-line driving signal DS. The gate electrode of the driving transistor TR1 is connected to a specific one of the terminals of the signal-level holding capacitor C1 as described above and also wired to the signal line SIG, which is connected to the horizontal selector 2, through the signal writing transistor TR5. Thus, the pixel circuit 7 is provided with a configuration in which, with the signal writing transistor TR5 controlled to enter a state of being turned on by the write scan-line driving signal WS, the signal-line driving signal Ssig asserted on the signal line SIG is applied to the specific terminal of the signal-level holding capacitor C1 and the gate electrode of the driving transistor TR1 by way of the signal writing transistor TR5 as a desired voltage. In this patent specification, the specific terminal of the signal-level holding capacitor C1 is a terminal connected to the gate electrode of the driving transistor TR1 and the signal writing transistor TR5 whereas the other terminal of the signal-level holding capacitor C1 is a terminal connected to the source electrode of the driving transistor TR1 and the anode electrode of the organic EL device 8.
As described above, in the pixel circuit 7, with the power switching transistor TR2 controlled to enter a state of being turned off by the drive scan-line driving signal DS, the current supplied to the driving transistor TR1 by way of the power switching transistor TR2 is cut off so that the drain-source current Ids flowing to the organic EL device 8 is also cut off as well. In this state, the pixel circuit 7 starts a no-light emission period. With the signal writing transistor TR5 controlled to enter a state of being turned on by the write scan-line driving signal WS, a high-level signal-line driving signal Ssig asserted on the signal line SIG is applied to the specific terminal of the signal-level holding capacitor C1 and the gate electrode of the driving transistor TR1 by way of the signal writing transistor TR5 so that a voltage appearing on the specific terminal of the signal-level holding capacitor C1 and the gate electrode of the driving transistor TR1 once rises. With the voltage on the specific terminal of the signal-level holding capacitor C1 and the gate electrode of the driving transistor TR1 rising, a voltage appearing on the other terminal of the signal-level holding capacitor C1, the source electrode of the driving transistor TR1 and the anode electrode of the organic EL device 8, which are connected to each other, also once rises as well. Since the electric charge accumulated on the other terminal of the signal-level holding capacitor C1 is discharged through the organic EL device 8, however, the voltage appearing on the other terminal of the signal-level holding capacitor C1, the source electrode of the driving transistor TR1 and the anode electrode of the organic EL device 8 is sustained at the threshold voltage of the organic EL device 8.
Then, in the pixel circuit 7, when the level of the signal-line driving signal Ssig asserted on the signal line SIG becomes lower, the voltage appearing on the specific terminal of the signal-level holding capacitor C1 and the gate electrode of the driving transistor TR1 also becomes lower as well. In addition, due to a coupling effect exhibited by the signal-level holding capacitor C1, the voltage appearing on the other terminal of the signal-level holding capacitor C1, the source electrode of the driving transistor TR1 and the anode electrode of the organic EL device 8 also becomes lower to a level not higher than the threshold voltage of the organic EL device 8 in a manner of being interlocked with the phenomenon showing that the voltage appearing on the specific terminal of the signal-level holding capacitor C1 and the gate electrode of the driving transistor TR1 is becoming lower.
With the level of the signal-line driving signal Ssig on the signal line SIG becoming high and low as described above, in the pixel circuit 7, a voltage applied between the two terminals of the signal-level holding capacitor C1 is set at a magnitude at least equal to the threshold voltage Vth of the driving transistor TR1 and a compensation preparing process preparing for a process of compensating a pixel circuit 7 for variations of the threshold voltage Vth of the driving transistor TR1 in the pixel circuit 7 from transistor to transistor is completed. In this patent specification, the process of compensating a pixel circuit for variations of the threshold voltage Vth of the driving transistor TR1 in the pixel circuit from transistor to transistor is referred to as a threshold-voltage variation compensation process which is below. In addition, in this patent specification, unless otherwise specified, the threshold-voltage variation compensation process is carried out right after the compensation preparing process.
Then, in the pixel circuit 7, the power switching transistor TR2 is controlled to enter a state of being turned on by the drive scan-line driving signal DS in order to start an operation to supply a current from the power supply for generating the power-supply voltage Vdd to the driving transistor TR1 by way of the power switching transistor TR2. With such an operation started, driven by the gate-source voltage Vgs of the driving transistor TR1, that is, driven by the voltage applied between the two terminals of the signal-level holding capacitor C1, the driving transistor TR1 gradually charges the other terminal of the signal-level holding capacitor C1 (that is, the terminal connected to the source electrode of the driving transistor TR1 and the anode electrode of the organic EL device 8) so that the voltage applied between the two terminals of the signal-level holding capacitor C1 gradually decreases. As the voltage applied between the two terminals of the signal-level holding capacitor C1 decreases to a magnitude equal to the threshold voltage Vth of the driving transistor TR1, the driving transistor TR1 stops the electrical charging operation. In this way, the pixel circuit 7 sets the voltage applied between the two terminals of the signal-level holding capacitor C1 at the threshold voltage Vth of the driving transistor TR1 in the aforementioned process of compensating a pixel circuit 7 for variations of the threshold voltage Vth of the driving transistor TR1 in the pixel circuit 7 from transistor to transistor.
The pixel circuit 7 operates over a plurality of periods in each of which the driving transistor TR1 gradually charges the other terminal of the signal-level holding capacitor C1 (that is, the terminal connected to the source electrode of the driving transistor TR1 and the anode electrode of the organic EL device 8) so that the voltage applied between the two terminals of the signal-level holding capacitor C1 is eventually set at a magnitude equal to the threshold voltage Vth of the driving transistor TR1 as described above. Each consecutive two of such charging periods to eventually set the voltage applied between the two terminals of the signal-level holding capacitor C1 at a magnitude equal to the threshold voltage Vth of the driving transistor TR1 sandwich a pause period determined in advance. If sufficient charging time can be allocated to the charging processes in one horizontal scan period, the series of charging process of eventually setting the voltage applied between the two terminals of the signal-level holding capacitor C1 at a magnitude equal to the threshold voltage Vth can be carried out after the compensation preparing process mentioned earlier in one horizontal scan period.
Then, in the pixel circuit 7, a gradation voltage indicating the luminance of light emitted by the organic EL device 8 is set on the gate electrode of the driving transistor TR1 via the signal writing transistor TR5. At that point, the gradation voltage is corrected in accordance with the threshold voltage Vth of the driving transistor TR1 and the corrected gradation voltage is newly set as a voltage applied between the two terminals of the signal-level holding capacitor C1 to replace the threshold voltage Vth which has been set so far as a voltage applied between the two terminals of the signal-level holding capacitor C1. In this patent specification, a process to set a gradation voltage indicating the luminance of light emitted by the organic EL device 8 on the gate electrode of the driving transistor TR1 by way of the signal writing transistor TR5 is referred to as a gradation-voltage setting operation.
In the pixel circuit 7, with the signal line SIG put in a state of being electrically connected to the gate electrode of the driving transistor TR1 by the signal writing transistor TR5 put in a state of being turned on, after the power supply for generating the power-supply voltage Vdd has output a current to the driving transistor TR1 by way of the power switching transistor TR2 put in a state of being turned on for a fixed period of time, the signal writing transistor TR5 is put in a state of being turned off and a light emission period is commenced while the gradation-voltage setting operation is ended.
In accordance with a configuration disclosed in Japanese Patent Laid-open No. 2007-133284, by carrying out the processing to compensate a pixel circuit for variations of the threshold voltage Vth of the driving transistor TR1 in the pixel circuit from transistor to transistor in a plurality of periods, every two of which sandwich the pause period mentioned before, the resolution of the image can be improved so that, even if sufficient time cannot be allocated to the processing to compensate a pixel circuit for variations of the threshold voltage Vth of the driving transistor TR1 in the pixel circuit from transistor to transistor in one horizontal scan period, sufficient time can be allocated to the compensation processing in a plurality of horizontal scan periods, in which the compensation processing is to be carried out, in order to allow the execution of the processing to compensate the pixel circuit for variations of the threshold voltage Vth of the driving transistor TR1 in the pixel circuit from transistor to transistor.
With the signal line SIG put in a state of being electrically connected to the gate electrode of the driving transistor TR1 by the signal writing transistor TR5 put in a state of being turned on, after the power supply for generating the power-supply voltage Vdd has output a current to the driving transistor TR1 by way of the power switching transistor TR2 put in a state of being turned on for a fixed period of time, the signal writing transistor TR5 is put in a state of being turned off. At the time the signal writing transistor TR5 is put in a state of being turned off, the larger the mobility of the driving transistor TR1 employed in a pixel circuit 7, the more the voltage applied between the two terminals of the signal-level holding capacitor C1 employed in the same pixel circuit 7 as the driving transistor TR1 can be reduced. Thus, it is possible to decrease luminance variations caused by the variations of the mobility of the driving transistor TR1 to appear as variations of the luminance of light emitted by the organic EL device employed in the same pixel circuit 7 as the driving transistor TR1 from pixel to pixel. In this patent specification, a process of decreasing luminance variations caused by the variations of the mobility of the driving transistor TR1 to appear as variations of the luminance of light emitted by the organic EL device employed in the same pixel circuit as the driving transistor TR1 from pixel to pixel is referred to as a mobility variation compensation process which is carried out while the gradation-voltage setting operation is being performed.
However, the configuration shown in the block diagram of FIG. 17 has a shortcoming that each pixel circuit 7 employs three NMOS transistors TR1, TR2 and TR5 which make the configuration complicated. As one of possible methods for overcoming this shortcoming, the power switching transistor TR2 for controlling the power supply serving as the source of the drain-source current Ids is eliminated. In this case, the power supply for supplying the drain-source current Ids to the driving transistor TR1 is controlled by the drive scanner 4B employed in the scan-line driving circuit 5.
FIG. 18 is a block diagram showing interconnections of sections employed in an image displaying apparatus 11 not employing the power switching transistor TR2. In the configuration shown in the block diagram of FIG. 18, each of configuration components identical with their respective counterparts employed in the image displaying apparatus 1 shown in the block diagram of FIG. 17 is denoted by the same reference numeral or notation as the counterpart. In addition, each of configuration components identical with their respective counterparts employed in the image displaying apparatus 1 shown in the block diagram of FIG. 17 is not explained in order to avoid duplications of descriptions. The image displaying apparatus 11 has an image displaying section 12 created on an insulating substrate determined in advance. In addition, the image displaying apparatus 11 also includes a signal-line driving circuit 13 and a scan-line driving circuit 14, which are provided at locations surrounding the image displaying section 12. The signal-line driving circuit 13 includes a horizontal selector (HSEL) 15 whereas the scan-line driving circuit 14 which includes a write scanner (WSCN) 16A and a drive scanner (DSCN) 16B.
Much like the horizontal selector 2 employed in the image displaying apparatus 1 shown in the block diagram of FIG. 17, the horizontal selector 15 employs a plurality of latch circuits for sequentially latching input image data D1. Each of the latch circuits is provided for one of signal lines SIG connected to the image displaying section 12. The input image data D1 latched in the latch circuits is apportioned to the signal lines SIG. The input image data D1 to be apportioned to any one of the signal lines SIG is converted into an analog signal in a digital-to-analog conversion process and asserted to the signal line SIG to serve as one of driving signals Vsig which sequentially show gradations of pixel circuits connected to the signal lines SIG. The horizontal selector 15 also outputs a predetermined reference voltage Vofs determined in advance alternately to the analog signals Vsig obtained as a result of the digital-to-analog conversion process. The horizontal selector 15 outputs a signal-line driving signal Ssig including the predetermined reference voltage Vofs and the gradation voltage Vsig to a signal line SIG for which the signal-line driving signal Ssig is generated.
Each of the write scanner 16A and the drive scanner 16B sequentially transfers a reference signal generated by a signal generation circuit not shown in the block diagram of FIG. 18 to scan lines to serve as a write scan-line driving signal WS and a drive scan-line driving signal DS respectively. To be more specific, the write scanner 16A asserts the write scan-line driving signal WS on a write scan line connected to the gate electrode of each transistor TR5 on a row corresponding to the write scan line whereas the drive scanner 16B asserts the drive scan-line driving signal DS on a drive scan line connected to the drain electrode of each transistor TR1 on a row corresponding to the drive scan line.
The image displaying section 12 includes pixel circuits 17 which are arranged to form a pixel matrix. The pixel circuit 17 has a configuration identical with the configuration of the pixel circuit 7 employed in the image displaying apparatus 1 shown in the block diagram of FIG. 17 except that the pixel circuit 17 does not employ the power switching transistor TR2 for controlling the Vdd generating power supply for outputting a current to the driving transistor TR1.
FIGS. 19A1 to 19F2 are timing charts referred to in explanation of operations carried out by the pixel circuit 17. It is to be noted that, in the following description, in order to make the explanation simple, it is assumed that the capacitance of a parasitic capacitor of the gate electrode of the driving transistor TR1 is sufficiently small in comparison with the capacitance of the signal-level holding capacitor C1 but the capacitance of the capacitive component Cp of the organic EL device 8 is sufficiently large in comparison with the capacitance of the signal-level holding capacitor C1. In addition, the image displaying apparatus 11 carries out the gradation-voltage setting operation to set the luminance of light emitted by each of pixel circuits 17 sequentially on a row-after-row basis, that is, one gradation-voltage setting operation carried out at one time on one pixel-matrix row, for every field. In FIGS. 19A1 to 19F2, reference notation i denotes a number assigned to a specific pixel-matrix row subjected to the process of setting the luminance of light emitted by a pixel circuit 17 on the specific pixel-matrix row and reference notation (i+1) denotes a number assigned to a next pixel-matrix row following the specific pixel-matrix row to serve as a next pixel-matrix row subjected next to the process of setting the luminance of light emitted by a pixel circuit 17 on the next pixel-matrix row. Each of the numbers i and (i+1) is also used as a subscript assigned to a signal appearing on a signal line SIG, a write scan line and a drive scan line, which pertain to the pixel-matrix row, assigned to a signal appearing to the gate or source electrode of the driving transistor TR1 on the pixel-matrix row or assigned to the pixel circuit 17 employing the organic EL device 8 on the pixel-matrix row. In addition, in FIGS. 19A1 to 19F2, the word “Preparation” is used to denote the period of a compensation preparing process of preparing for a process of compensating the pixel circuit for variations of the threshold voltage Vth of the driving transistor TR1 in the pixel circuit from transistor to transistor. As described before, in the compensation preparing process, the voltage appearing between the two terminals of the signal-level holding capacitor C1 is set at a magnitude at least equal to the threshold voltage Vth of the driving transistor TR1 employed in the same pixel circuit 17 as the signal-level holding capacitor C1. Then, after the compensation preparing process has been completed, a threshold-voltage variation compensation process of changing the voltage appearing between the two terminals of the signal-level holding capacitor C1 from the magnitude set in the compensation preparing process as the magnitude at least equal to the threshold voltage Vth of the driving transistor TR1 to a magnitude equal to the threshold voltage Vth of the driving transistor TR1 employed in the same pixel circuit 17 as the signal-level holding capacitor C1 is carried out once in one period of time. In FIGS. 19A1 to 19F2, the time period of this threshold-voltage variation compensation process is denoted by the phrase “Vth compensation.” After the threshold-voltage variation compensation process has been completed, a mobility variation compensation process is carried out to compensate the pixel circuit 17 for variations of the mobility μ of the driving transistor TR1 in the pixel circuit 17 from transistor to transistor. In FIGS. 19A1 to 19F2, the time period of this mobility variation compensation process is denoted by the phrase “μ compensation.”
As shown in FIGS. 19A1 to 19F2, at a time t1, each pixel circuit 17 starts a no-light emission period T1 during which the light emission of the organic EL device 8 is stopped. At the time t1, the voltage of the drive scan-line driving signal DS drops from a power-supply voltage Vdd at which the drive scan-line driving signal DS is set during a light emission period T2 to another reference voltage Vss2 as depicted by a timing chart of FIG. 19B1 for the ith pixel-matrix row. By the way, a timing chart of FIG. 19B2 is the timing chart of the drive scan-line driving signal DS on the (i+1)th pixel-matrix row. As a matter of fact, in the following description, a prefix “1” appended to a reference notation to form a reference notation such as FIG. 19B1 indicates that the timing chart is the timing chart of a signal or a pixel circuit 17 including an organic EL device 8 on the ith pixel-matrix row. On the other hand, a prefix “2” appended to a reference notation to form a reference notation such as FIG. 19B2 indicates that the timing chart is the timing chart of a signal or a pixel circuit 17 including an organic EL device 8 on the (i+1)th pixel-matrix row. The other reference voltage Vss2 is a voltage lower than the sum of a cathode voltage Vss1 of the organic EL device 8 and the threshold voltage of the organic EL device 8. Thus, in the pixel circuit 17, the electrode of the driving transistor TR1 receiving the drive scan-line driving signal DS functions as the source electrode and the voltage appearing on the anode electrode of the organic EL device 8 becomes lower, ending the light emission of the organic EL device 8. In addition, electric charge accumulated in the signal-level holding capacitor C1 is discharged from the other terminal of the signal-level holding capacitor C1 through the driving transistor TR1. Thus, the other terminal of the signal-level holding capacitor C1 is set at the other reference voltage Vss2 as depicted by timing charts of FIGS. 19E1 and 19E2. As described earlier, the other terminal of the signal-level holding capacitor C1 is the terminal connected to the anode electrode of the organic EL device 8. Each of the timing charts of FIGS. 19E1 and 19E2 is shown as the timing chart of a source signal Vs appearing on the source electrode of the driving transistor TR1.
In addition, at a time in the period of a compensation preparing process, in the pixel circuit 17, the signal-line driving signal Ssig asserted on the signal line SIG is lowered to the predetermined reference voltage Vofs as depicted by a timing chart of FIG. 19C and, then, the write scan-line driving signal WS is raised in order to put the signal writing transistor TR5 in a state of being turned on as depicted by timing charts of FIGS. 19A1 and 19A2. Thus, the gate voltage Vg of the driving transistor TR1 in the pixel circuit 17 is set at the predetermined reference voltage Vofs appearing on the signal line SIG as depicted by timing charts of FIGS. 19D1 and 19D2 and the voltage appearing between the two terminals of the signal-level holding capacitor C1 is set at (Vofs−Vss2). In the pixel circuit 17, the predetermined reference voltage Vofs and the other reference voltage Vss2 are set at such levels that the voltage (Vofs−Vss2) appearing between the two terminals of the signal-level holding capacitor C1 is greater than the threshold voltage Vth of the driving transistor TR1, that is, the relation (Vss2<(Vofs−Vth)) is satisfied.
Thus, in the pixel circuit 17, the voltage appearing between the two terminals of the signal-level holding capacitor C1 is set at (Vofs−Vss2) which is a voltage greater than the threshold voltage Vth of the driving transistor TR1 in a compensation preparing process of preparing for a threshold-voltage (Vth) variation compensation process of setting the voltage appearing between the two terminals of the signal-level holding capacitor C1 at the threshold voltage Vth of the driving transistor TR1 as depicted by timing charts of FIGS. 19F1 and 19F2. It is to be noted that, in consequence, the predetermined reference voltage Vofs needs to be a voltage that does not put the driving transistor TR1 in a state of being turned on after the execution of the threshold-voltage variation compensation process of compensating a pixel circuit for variations of the threshold voltage Vth of the driving transistor TR1 in the pixel circuit from transistor to transistor. That is to say, the relation (Vofs<Vss1+Vtholed+Vth) needs to be satisfied where reference notation Vthoeld denotes the threshold voltage of the organic EL device 8.
Then, at a time t2 in a period of sustaining the signal-line driving signal Ssig appearing on the signal line SIG at the predetermined reference voltage Vofs, with the signal writing transistor TR5 in the pixel circuit 17 sustained in a state of being turned on as it is, the drive scan-line driving signal DS is raised to the power-supply voltage Vdd provided for the light emission period in order to start an operation to supply a drain-source current Ids to the driving transistor TR1 as depicted by timing charts of FIGS. 19B1 and 19B2. Subsequently, at a point of time immediately before the level of the signal-line driving signal Ssig appearing on the signal line SIG is set at the gradation voltage Vsig, the write scan-line driving signal WS is lowered in order to put the driving transistor TR1 in a state of being turned off.
With the pixel circuit 17 put in this state, a charging current is flowing from the power supply for generating the power-supply voltage Vdd to the other terminal of the signal-level holding capacitor C1 by way of the driving transistor TR1 on the condition that the voltage appearing between the two terminals of the signal-level holding capacitor C1 is greater than the threshold voltage Vth of the driving transistor TR1 so that the source voltage Vs of the driving transistor TR1 is gradually increasing to such a level that the voltage appearing between the two terminals of the signal-level holding capacitor C1 becomes equal to the threshold voltage Vth of the driving transistor TR1 as depicted by timing charts of FIGS. 19E1 and 19E2. As described before, the other terminal of the signal-level holding capacitor C1 is the terminal connected to the anode electrode of the organic EL device 8. In the timing diagram of FIGS. 19A1 to 19F2, the voltage appearing between the two terminals of the signal-level holding capacitor C1 is the difference between the gate voltage Vg shown in a timing chart of FIG. 19D1 or 19D2 and the source voltage Vs shown in the timing chart of FIG. 19E1 or 19E2. That is to say, in the pixel circuit 17, the voltage appearing between the two terminals of the signal-level holding capacitor C1 is gradually approaching the threshold voltage Vth of the driving transistor TR1. As the voltage appearing between the two terminals of the signal-level holding capacitor C1 becomes equal to the threshold voltage Vth of the driving transistor TR1, the source voltage Vs of the driving transistor TR1 stops rising. In this way, the voltage appearing between the two terminals of the signal-level holding capacitor C1 is set at the threshold voltage Vth of the driving transistor TR1 in the pixel circuit 17 in an operation referred to as the so-called threshold-voltage variation compensation process.
Then, in the pixel circuit 17, at a time t3, the level of the signal-line driving signal Ssig appearing on the signal line SIG is set at the gradation voltage Vsig generated for the pixel circuit 17. At the same time, the write scan-line driving signal WS is raised to a high level in order to put the signal writing transistor TR5 in a state of being turned on as depicted by timing charts of FIGS. 19A1 and 19A2. With the signal writing transistor TR5 put in a state of being turned on, the gate electrode of the driving transistor TR1 is electrically connected to the signal line SIG. At a point of time upon the lapse of a period Tμ determined in advance, the write scan-line driving signal WS is decreased to a low level in order to electrically disconnect the gate electrode of the driving transistor TR1 from the signal line SIG. In this state, the gradation voltage Vsig which has been appearing as the signal-line driving signal Ssig on the signal line SIG is held in the specific terminal of the signal-level holding capacitor C1. As described previously, the specific terminal of the signal-level holding capacitor C1 is the terminal connected to the gate electrode of the driving transistor TR1. Since the voltage appearing between the two terminals of the signal-level holding capacitor Cl has been set at the threshold voltage Vth of the driving transistor TR1 employed in the pixel circuit 17, the threshold voltage Vth set between the two terminals of the signal-level holding capacitor C1 is used for compensating the pixel circuit 17 for variations of the threshold voltage Vth of the driving transistor TR1 in the pixel circuit 17 from transistor to transistor in setting the voltage appearing between the two terminals of the signal-level holding capacitor C1 at a voltage according to the gradation voltage Vsig. Thus, the image displaying apparatus 11 is capable of getting rid of image-quality deteriorations caused by the variations of the threshold voltage Vth of the driving transistor TR1 from transistor to transistor.
With the gate electrode of the driving transistor TR1 put in a state of being electrically connected to the signal line SIG during the period Tμ cited above, the power-supply voltage Vdd is applied to the driving transistor TR1. Thus, the source voltage Vs of the driving transistor TR1 is gradually rising in accordance with the magnitude of the drain-source current Ids which depends on the gate-source voltage Vgs of the driving transistor TR1 as shown in Equation (1). In addition, the speed at which the source voltage Vs of the driving transistor TR1 is rising is also determined by the mobility μ of the driving transistor TR1 as is obvious from the equation. To be more specific, the larger the mobility μ of the driving transistor TR1, the higher the speed at which the source voltage Vs of the driving transistor TR1 is rising. As the source voltage Vs rises, however, the gate-source voltage Vgs decreases, making it difficult for the drain-source current Ids to flow through the driving transistor TR1.
Thus, in the pixel circuit 17, there is observed a phenomenon in which the larger the mobility μ of the driving transistor TR1, the larger the decrease made during the period Tμ as a decrease of the voltage appearing between the two terminals of the signal-level holding capacitor C1. This phenomenon occurs in the so-called mobility compensation process of compensating the pixel circuit 17 for variations of mobility μ of the driving transistor TR1 in the pixel circuit 17 from transistor to transistor in order to prevent the quality of the image from deteriorating. It is to be noted that the drain-source current Ids flowing through the driving transistor TR1 during the period Tμ is expressed by Equation (4) as follows:Ids=β/2·(1/Vsig+β/2·Tμ/C)−2 C=C1+Coled  (4)
In the above equation, reference notation C1 denotes the capacitance of the signal-level holding capacitor C1 whereas reference notation Coled denotes the capacitance of the capacitive component Cp of the organic EL device 8.
Thus, the period prior to the time t2 is the period of the compensation preparing process of setting the voltage appearing between the two terminals of the signal-level holding capacitor C1 at a magnitude at least equal to the threshold voltage Vth of the driving transistor TR1. The period between the time t2 and a point of time immediately leading ahead of the time t3 is the period of a threshold-voltage (Vth) variation compensation process of setting the voltage appearing between the two terminals of the signal-level holding capacitor C1 at a magnitude equal to the threshold voltage Vth of the driving transistor TR1. The period between the times t3 and t4 is the period of the gradation-voltage setting operation to store the voltage of a gradation voltage Vsig in the signal-level holding capacitor C1 and the mobility variation compensation process of reducing the voltage appearing between the two terminals of the signal-level holding capacitor C1 to a level dependent on the mobility μ of the driving transistor TR1.
In the pixel circuit 17, the write scan-line driving signal WS is decreased to a low level at a time t4 in order to put the signal writing transistor TR5 in a state of being turned off so that the gate electrode of the driving transistor TR1 is put in a state of being electrically disconnected from the signal line SIG, that is a state of being floated. At this point of time, a light emission period T2 is commenced. In this light emission period T2, the organic EL device 8 is driven to emit light by the drain-source current Ids which is flowing through the driving transistor TR1 in accordance with the voltage appearing between the two terminals of the signal-level holding capacitor C1 to serve as the gate-source voltage Vgs of the driving transistor TR1. It is to be noted that, during this light emission period T2, the drain-source current Ids is accumulating electric charge in the capacitive component Cp of the organic EL device 8, raising the source voltage Vs of the driving transistor TR1 from a level attained at the end of the period Tμ and, due to an operation caused by the coupling effect of the signal-level holding capacitor C1 to appear as a bootstrap operation of the signal-level holding capacitor C1, the gate voltage Vg also rises as well from a level attained at the end of the period Tμ. As a result, the organic EL device 8 starts to emit light. In the course of time, the gate voltage Vg and source voltage Vs of the driving transistor TR1 stop rising and each stay at a fixed level. It is to be noted that, in order to operate the driving transistor TR1 in a saturated region during the light emission period T2, the power-supply voltage Vdd needs to be set at such a level that the relation (Vdd>Vthoeld+Vgs−Vth) given before is satisfied.
Thus, in the typical configuration of the image displaying apparatus 11 shown in the block diagram of FIG. 18, as shown in FIGS. 20A to 20E, reference notation 1H denotes a horizontal scan period during which the compensation preparing process, the threshold-voltage variation compensation process, the mobility variation compensation process and the gradation-voltage setting operation, which have been described above, are carried out on each of pixel circuits 17 on consecutive pixel-matrix rows. The compensation preparing process, the threshold-voltage variation compensation process, the mobility variation compensation process and the gradation-voltage setting operation are carried out on pixel circuits 17 of the ith pixel-matrix row, pixel circuits 17(i+1) of the (i+1)th pixel-matrix row, pixel circuits 17(i+2) of the (i+2)th pixel-matrix row, pixel circuits 17(i+3) of the (i+3)th pixel-matrix row and so on sequentially on a row-after-row basis, that is, one gradation-voltage setting operation carried out at one time on one pixel-matrix row, in order to set gradations in the pixel circuits 17, the pixel circuits 17(i+1), the pixel circuits 17(i+2), the pixel circuits 17(i+3) and so on so as to display a desired image on the image displaying section 12. It is to be noted that, in FIGS. 20A to 20E, reference notation “Compensate” denotes the compensation preparing process and the threshold-voltage variation compensation process whereas reference notation “Write” denotes the gradation-voltage setting operation which includes the mobility variation compensation process as described above by referring to FIGS. 19A1 to 19F2. As described above by referring to FIGS. 19A1 to 19F2, the gradation-voltage setting operation is an operation to hold the gradation voltage Vsig appearing on the signal line SIG as the signal-line driving signal Ssig in the signal-level holding capacitor C1.
Japanese Patent Laid-open No. 2002-514320, Japanese Patent Laid-open No. 2004-133240 and Japanese Patent Laid-open No. 2004-246204 propose a method for compensating a pixel circuit for variations of the threshold voltage of the driving transistor in the pixel circuit from transistor to transistor by correcting a gradation voltage in accordance with a voltage set in advance in a signal-level holding capacitor as a voltage dependent on the threshold voltage of the driving transistor and setting the corrected gradation voltage in the driving transistor as a voltage appearing between the gate and source electrodes of the driving transistor in a pixel circuit having the configuration described above.
In addition, Japanese Patent Laid-open No. 2005-345722, Japanese Patent Laid-open No. 2006-215213 and Japanese Patent Laid-open No. 2007-133282 propose a method for compensating a pixel circuit for variations of the threshold voltage of the driving transistor in the pixel circuit from transistor to transistor in the same way.
If the compensation preparing process, the threshold-voltage variation compensation process, the mobility variation compensation process and the gradation-voltage setting operation are carried out on pixel circuits 17 of the ith pixel-matrix row, pixel circuits 17(i+1) of the (i+1)th pixel-matrix row, pixel circuits 17(i+2) of the (i+2)th pixel-matrix row, pixel circuits 17(i+3) of the (i+3)th pixel-matrix row and so on sequentially on a row-after-row basis, that is, one gradation-voltage setting operation carried out at one time on one pixel-matrix row, within every horizontal scan period 1H in order to set gradations in the pixel circuits 17, the pixel circuits 17(i+1), the pixel circuits 17(i+2), the pixel circuits 17(i+3) and so on so as shown in FIGS. 20A to 20E, however, it is feared that sufficient time cannot be allocated to the threshold-voltage variation compensation process of compensating a pixel circuit for variations of the threshold voltage Vth of the driving transistor in the pixel circuit from transistor to transistor in the case of a high image displaying resolution of the image displaying apparatus. This is because, in the case-of a high image displaying resolution of the image displaying apparatus, the length of the horizontal scan period becomes short.
In order to solve the problem raised by the method explained above by referring to FIGS. 20A to 20E, as one of conceivable solution methods, a typical method to be explained below by referring to FIGS. 21A to 21E has been proposed. In accordance with this typical conceivable solution method, after the threshold-voltage variation compensation process of compensating a pixel circuit for variations of the threshold voltage Vth of the driving transistor in the pixel circuit from transistor to transistor on a plurality of particular consecutive pixel-matrix rows at the same time, the gradation-voltage setting operation is carried out on pixel circuits of each of the particular consecutive pixel-matrix rows. The number of particular consecutive pixel-matrix rows subjected to the threshold-voltage variation compensation process carried out at the same time to compensate a pixel circuit for variations of the threshold voltage Vth of the driving transistor in the pixel circuit from transistor to transistor and the gradation-voltage setting operation carried out at separated times after the execution of the threshold-voltage variation compensation process is 2. To put it concretely, as depicted by a timing chart of FIG. 22C given as a comparison with the timing chart of FIG. 19C, the predetermined reference voltage Vofs, the gradation voltage Vsig (i) representing the gradation of a pixel circuit on the ith pixel-matrix row and the gradation voltage Vsig (i+1) representing the gradation of a pixel circuit on the next (i+1)th pixel-matrix row immediately following the ith pixel-matrix row are asserted successively on their respective signal lines Sig as driving signals Ssig. That is to say, in a period of asserting the predetermined reference voltage Vofs on the signal line SIG as the signal-line driving signal Ssig, each of the compensation preparing process and the threshold-voltage variation compensation process of compensating the pixel circuit for variations of the threshold voltage Vth of the driving transistor in the pixel circuit from transistor to transistor is carried out on the driving transistors of the two consecutive ith and (i+1)th pixel-matrix rows at the same time. Then, in a period of asserting the gradation voltage Vsig (i) on the signal line SIG as the signal-line driving signal Ssig, the gradation-voltage setting operation is carried out on the ith pixel-matrix row and, in the following period of asserting the gradation voltage Vsig (i+1) on the signal line SIG as the signal-line driving signal Ssig, the gradation-voltage setting operation is carried out on the next (i+1)th pixel-matrix row.
If the threshold-voltage variation compensation process of compensating a pixel circuit for variations of the threshold voltage Vth of the driving transistor in the pixel circuit from transistor to transistor on a plurality of consecutive pixel-matrix rows at the same time, however, it is known that there are subtle differences in light luminance between the pixel-matrix rows and, as a result, horizontal-direction cords from are generated, causing the quality of the image to deteriorate.